1. Technical Field
The present invention relates to information handling or data processing systems, and in particular to comparator circuits for use therein to determine whether two addresses are equal or not equal.
2. Background Art
The design of a typical computer data processing system or information handling system requires the use of a comparator circuit array for comparing two or more addresses to determine whether the addresses are equal to each other or not equal to each other. For example, read addresses are compared to write addresses for access addressable registers such as a general purpose register ("GPR"). If the read and write addresses are equal, that is the system wishes to read from and write to the same address in the GPR at the same time, a bypass of the read operation may become necessary. Such computer data processing systems or information handling systems using dynamic-based circuitry require a positive logic signal indicating whether two addresses are equal and a positive logic signal indicating whether two addresses are not equal at virtually the same time.
Conventional comparator circuits for determining whether two addresses are equal or not equal require addresses which are encoded into a dual rail format. In other words, these circuits require the true and complement of the bits making up the addresses to be compared. The conventional comparator circuit for determining whether two addresses are equal utilizes an exclusive nor (XNOR) gate that receives as inputs the true and complement of the addresses to be compared. The conventional comparator circuit for determining whether two addresses are not equal utilizes an exclusive or (XOR) gate that receives as inputs the true and complement of the addresses to be compared. These conventional prior art comparator circuits do not work for specially encoded addresses, i.e., addresses not utilizing the dual rail format or true and complement format.
Other encoding schemes for use within computer data processing or information handling system have been developed to decrease overall power consumption and increase noise margin. In particular an encoded scheme for mapping two bits to four bits wherein only one of the four bits is "on" or in a high state (logical "1" as opposed to "0") at any given time has been developed. What is needed is a comparator circuit for comparing two addresses which are represented by such a two bit to four bit encoded scheme to determine whether the two addresses are equal or not equal.